A semiconductor memory device is under developing, which includes three-dimensionally arranged memory cells. For example, a NAND type memory device includes a plurality of word lines stacked on a source line and a semiconductor pillar extending therethrough, and the memory cells are disposed at parts where the semiconductor pillar crosses the respective word lines. The semiconductor pillar is electrically connected to the source line, and the memory cells are driven by a bias applied to the semiconductor pillar via the source line and biases applied to the respective word lines. In the memory device having such a structure, for example, when the electric resistance along the current path in the source line, which leads to the semiconductor pillar, is large, some drawbacks may be arisen such as reduction of the ON current for reading data out from the memory cells.